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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT648 Octal bus transceiver/register; 3-state; inverting
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state; inverting
FEATURES * Independent register for A and B buses * Multiplexed real-time and stored data * Output capability: bus driver * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT648 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT648 consist of bus transceiver circuits with 3-state inverting outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the internal registers. Data on the "A" or "B" QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns
74HC/HCT648
bus will be clocked into the registers as the appropriate clock (CPAB and CPBA) goes to a HIGH logic level. Output enable (OE) and direction (DIR) inputs are provided to control the transceiver function. In the transceiver mode, data present at the high-impedance port may be stored in either the "A" or "B" register, or in both. The select source inputs (SAB and SBA) can multiplex stored and real-time (transparent mode) data. The direction (DIR) input determines which bus will receive data when OE is active (LOW). In the isolation mode (OE = HIGH), "A" data may be stored in the "B" register and/or "B" data may be stored in the "A" register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. The "648" is functionally identical to the "646", but has inverting data paths.
TYPICAL SYMBOL tPHL/ tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay An, Bn to Bn, An maximum clock frequency input capacitance power dissipation capacitance per channel notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 11 75 3.5 30 HCT 11 88 3.5 31 ns MHz pF pF UNIT
December 1990
2
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state; inverting
PIN DESCRIPTION PIN NO. 1 2 3 4, 5, 6, 7, 8, 9, 10, 11 12 20, 19, 18, 17, 16, 15, 14, 13 21 22 23 24 SYMBOL CPAB SAB DIR A0 to A7 GND B0 to B7 OE SBA CPBA VCC NAME AND FUNCTION
74HC/HCT648
A to B clock input (LOW-to-HIGH, edge-triggered) select A to B source input direction control input A data inputs/outputs ground (0 V) B data inputs/outputs output enable input (active LOW) select B to A source input B to A clock input (LOW-to-HIGH, edge-triggered) positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
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Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state; inverting
74HC/HCT648
Fig.4 Functional diagram.
FUNCTION TABLE INPUTS (1) OE H H L L L L Notes 1. H = HIGH voltage level L = LOW voltage level X = don't care = LOW-to-HIGH level transition 2. The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock inputs. DIR X X L L H H CPAB H or L X X X H or L CPBA H or L X H or L X X X X X X L H SAB X X L H X X SBA DATA I/O (2) FUNCTION A0 TO A7 input output input B0 TO B7 input input output isolation store A and B data real-time B data to A bus stored B data to A bus real-time A data to B bus stored A data to B bus
December 1990
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Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state; inverting
74HC/HCT648
Fig.5 Logic diagram.
December 1990
5
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state; inverting
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 min. tPHL/ tPLH propagation delay An, Bn to Bn, An propagation delay CPAB, CPBA to Bn, An propagation delay SAB, SBA to Bn, An 3-state output enable time OE to An, Bn 3-state output disable time OE to An, Bn 3-state output enable time DIR to An, Bn 3-state output disable time DIR to An, Bn output transition time typ. 39 14 11 74 27 22 55 20 16 52 19 15 61 22 18 52 19 15 55 20 16 14 5 4 80 16 14 25 9 7 0 0 0 6 2 2 22 68 81 max. 135 27 23 230 46 39 190 38 32 175 35 30 175 35 30 175 35 30 175 35 30 60 12 10 100 20 17 75 15 13 45 9 8 4.8 24 28 6 -40 to +85 min. max. 170 34 29 290 58 49 240 48 41 220 44 37 220 44 37 220 44 37 220 44 37 75 15 13 120 24 20 90 18 15 55 11 9 4.0 20 24 -40 to +125 min. max. 205 41 35 345 69 59 285 57 48 265 53 45 265 53 45 265 53 45 265 53 45 90 18 15 ns UNIT
74HC/HCT648
TEST CONDITIONS VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0
WAVEFORMS
Fig.6
tPHL/ tPLH
ns
Fig.7
tPHL/ tPLH
ns
Fig.8
tPZH/ tPZL
ns
Fig.9
tPHZ/ tPLZ
ns
Fig.9
tPZH/ tPZL
ns
Fig.10
tPHZ/ tPLZ
ns
Fig.10
tTHL/ tTLH
ns
Fig.6 and Fig.8
tW
clock pulse width HIGH or LOW CPAB or CPBA
ns
Fig.7
tsu
60 set-up time 12 An, Bn to CPAB, CPBA 10 35 hold time 7 An, Bn to CPAB, CPBA 6 maximum clock pulse frequency 6.0 30 35
ns
Fig.7
th
ns
Fig.7
fmax
MHz
Fig.7
December 1990
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state; inverting
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI Note to HCT types
74HC/HCT648
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT SAB, SBA A0 to A7; and B0 to B7;
UNIT LOAD COEFFICIENT 0.60 0.75
INPUT CPAB; CPBA; OE DIR
UNIT LOAD COEFFICIENT 1.50 1.50 1.25
December 1990
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Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state; inverting
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 min. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPZH/ tPZL propagation delay An, Bn to Bn, An propagation delay CPAB, CPBA to Bn, An propagation delay SAB, SBA to Bn, An 3-state output enable time OE to An, Bn 3-state output disable time OE to An, Bn 3-state output enable time DIR to An, Bn 3-state output disable time DIR to An, Bn output transition time clock pulse width HIGH or LOW CPAB or CPBA set-up time An, Bn to CPAB, CPBA hold time An, Bn to CPAB, CPBA maximum clock pulse frequency 16 typ. 14 25 20 21 max. 27 46 38 40 -40 to +85 min. max. 34 58 48 50 -40 to +125 min. max. 41 69 57 60 ns ns ns ns UNIT
74HC/HCT648
TEST CONDITIONS VCC (V) 4.5 4.5 4.5 4.5
WAVEFORMS
Fig.6 Fig.7 Fig.8 Fig.9
tPHZ/ tPLZ
20
35
44
53
ns
4.5
Fig.9
tPZH/ tPZL
20
40
50
60
ns
4.5
Fig.10
tPHZ/ tPLZ
21
35
44
53
ns
4.5
Fig.10
tTHL/ tTLH tW
5 7
12 20
15 24
18
ns ns
4.5 4.5
Fig.6 and Fig.8 Fig.7
tsu th fmax
12 5 30
2 0 80
15 5 24
18 5 20
ns ns ns
4.5 4.5 MHz
Fig.7 Fig.7 Fig.7
December 1990
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Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state; inverting
AC WAVEFORMS
74HC/HCT648
(1)
HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the input An, Bn to output Bn, An propagation delays and the output transition times.
(1)
HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7
Waveforms showing the An, Bn to CPAB, CPBA set-up and hold times, clock CPAB, CPBA pulse width, maximum clock pulse frequency and the CPAB, CPBA to output Bn, An propagation delays.
(1)
HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the input SAB, SBA to output Bn, An propagation delays and output transition times.
December 1990
9
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state; inverting
74HC/HCT648
(1)
HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the input OE to output An, Bn 3-state enable and disable times.
(1)
HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the input DIR to output An, Bn 3-state enable and disable times.
December 1990
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Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state; inverting
APPLICATION INFORMATION
74HC/HCT648
Fig.11 Data storage from A and/or B bus.
Fig.12 Real-time transfer from bus A to bus B.
Fig.13 Real-time transfer from bus B to bus A.
December 1990
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Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state; inverting
PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
74HC/HCT648
December 1990
12

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